The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to asymmetric source/drain junctions for low power semiconductor-on-insulator (SOI) devices.
Demands for increased performance, functionality and manufacturing economy for integrated circuits have resulted in extreme integration density to reduce signal propagation time and increase noise immunity while increasing the number of circuits and devices that can be formed on a chip or wafer by a single sequence of processes. Scaling of devices to small sizes has also restricted operating margins and required increased uniformity of electrical characteristics of semiconductor devices on a chip.
To satisfy this latter criterion, semiconductor-on-insulator, or more specifically silicon-on-insulator (SOI) wafers have been used to exploit the improved quality of monocrystalline silicon provided thereby in an active layer formed on an insulator over a bulk silicon “handling” substrate. Similar attributes can be developed in similar structures of other semiconductor materials and alloys thereof. The improved quality of the semiconductor material of the active layer allows transistors and other devices to be scaled to extremely small sizes with good uniformity of electrical properties.
Unfortunately, the existence of the insulator layer that supports the development of the improved quality of semiconductor material also presents a problem known in the art as the floating body effect in transistor structures. The floating body effect is specific to transistors formed on substrates having an insulator layer. The neutral floating body is electrically isolated by source/drain and halo extension regions that form oppositely poled diode junctions at the ends of the transistor conduction channel and floating body while the gate electrode is insulated from the conduction channel through a dielectric. The insulator layer in the substrate completes insulation of the conduction channel and thus prevents discharge of any charge that may develop in the floating body. Charge injection into the neutral body when the transistor is not conducting develops voltages in the conduction channel in accordance with the source and drain diode characteristics.
The voltage developed due to charge collection in the transistor conduction channel has the effect of altering the switching threshold of the transistor. This effect, in turn, alters the signal timing and signal propagation speed since any transistor will have a finite slew rate and the rise and fall time of signals is not instantaneous even when gate capacitance is very small. Therefore, the diode characteristics of the source and drain must be tailored to limit charge build-up in the floating body.
To do so, the diode junctions may be made somewhat leaky to allow the floating body of the transistor to be discharged to an acceptable degree. However, since field effect transistors are generally formed symmetrically with identical source and drain impurity structures, development of such a characteristic reduces the ratio of resistance of the “on” and “off” states of the transistor, often referred to as the on/off ratio. A large on/off ratio is desirable to support maximum circuit fan out (the number of transistor gates a transistor can drive with acceptable switching speed) and to provide maximum signal voltage swing close to the power supply voltage. Therefore, there is a trade-off between limitation of floating body effects and maintaining a suitable on/off ratio. In addition, leaky junctions, particularly on the drain side, significantly increase leakage current and therefore total power consumption.